FPGA-Based Snake Game (VHDL & Nios II)

Description

This project demonstrates a hardware-software co-design approach to the classic Snake game using an Intel/Altera FPGA. The system architecture utilizes a Nios II soft-core processor to handle game logic and scoring, interfaced with custom VHDL peripherals for real-time hardware control.

• Logic & Control: Developed in C within the Nios II Eclipse environment, managing collision detection, speed scaling, and scoring.

• Hardware Interfacing: Designed custom VHDL modules in Quartus to drive an 8x12 LED Matrix (game arena) and a  LCD display.

• I/O: Real-time user input handled via physical push-buttons mapped to PIO (Parallel I/O) cores.